Sciweavers

5672 search results - page 24 / 1135
» Design techniques for low-power systems
Sort
View
VLSID
2007
IEEE
104views VLSI» more  VLSID 2007»
16 years 2 months ago
Customization of Register File Banking Architecture for Low Power
Register file banking is an effective alternative to monolithic register files in embedded processor based systems. In this work, we propose techniques for performing application s...
Rakesh Nalluri, Rohan Garg, Preeti Ranjan Panda
VTC
2006
IEEE
134views Communications» more  VTC 2006»
15 years 7 months ago
Ultra Low-Power Digital Demodulators for Short Range Applications
— In this paper we present extremely flexible and low power digital binary ASK, PSK, and FSK demodulator architectures for short-range applications that uses limiter amplifier (i...
Mehmet R. Yuce, Ahmet Tekin
COMPCON
1994
IEEE
15 years 6 months ago
Low Power Hardware for a High Performance PDA
The first product in the Newton family operates under severe constraints in the areas of performance, cost, heat dissipation, power consumption, scalability, size and weight. This...
Michael Culbert
114
Voted
ISLPED
1999
ACM
131views Hardware» more  ISLPED 1999»
15 years 6 months ago
Challenges in clockgating for a low power ASIC methodology
Gating the clock is an important technique used in low power design to disable unused modules of a circuit. Gating can save power by both preventing unnecessary activiiy in the lo...
David Garrett, Mircea R. Stan, Alvar Dean
104
Voted
ERSA
2006
99views Hardware» more  ERSA 2006»
15 years 3 months ago
Low Power Programmable FIR Filtering IP Cores Targeting System-on-a-Reprogrammable-Chip (SoRC)
- This paper presents the design and implementation methodology of some low power programmable FIR filtering IP cores targeting SoRC and compares their performance in term of area,...
Muhammad Akhtar Khan, Abdul Hameed, Ahmet T. Erdog...