5672 search results - page 27 / 1135 » Design techniques for low-power systems |
126
click to vote
ICCAD
1996
IEEE
15 years 6 months ago
1996
IEEE
In this paper we present an ecient technique to reduce the switching activity in a CMOS combinational logic network based on local logic transformations. These transformations con...
102
click to vote
ASPDAC
2005
ACM
15 years 3 months ago
2005
ACM
In modern VLSI designs, the increasingly severe power problem requests to minimize clock routing wirelength so that both power consumption and power supply noise can be alleviated...
115
Voted
ISCAS
2006
IEEE
15 years 8 months ago
2006
IEEE
Extremely low power consumption is the critical constraint for designing implantable neural decoders that inter- Desired face directly with the nervous system. Typically a system w...
126
Voted
ITC
2003
IEEE
15 years 7 months ago
2003
IEEE
In a scan-based system with a large number of flip-flops, a major component of power is consumed during scanshift and clocking operation in test mode. In this paper, a novel scan-...
115
click to vote
HPCC
2007
Springer
15 years 8 months ago
2007
Springer
Abstract. Low-power design became crucial with the widespread use of the embedded systems, where a small battery has to last for a long period. The embedded processors need to efï¬...