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» Design techniques for low-power systems
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133
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ISSS
2000
IEEE
127views Hardware» more  ISSS 2000»
15 years 6 months ago
Lower Bound Estimation for Low Power High-Level Synthesis
This paper addresses the problem of estimating lower bounds on the power consumption in scheduled data flow graphs with a fixed number of allocated resources prior to binding. T...
Lars Kruse, Eike Schmidt, Gerd Jochens, Ansgar Sta...
JCM
2008
70views more  JCM 2008»
15 years 1 months ago
Reed-Solomon Codes for Low Power Communications
Power consumption is a critical issue for many applications running on autonomous battery operated devices. In the context of low power communications, the use of Forward Error Cor...
Lionel Biard, Dominique Noguet
105
Voted
ICCD
2002
IEEE
108views Hardware» more  ICCD 2002»
15 years 10 months ago
Low Power Mixed-Mode BIST Based on Mask Pattern Generation Using Dual LFSR Re-Seeding
Low power design techniques have been employed for more than two decades, however an emerging problem is satisfying the test power constraints for avoiding destructive test and im...
Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nic...
CODES
2004
IEEE
15 years 5 months ago
A loop accelerator for low power embedded VLIW processors
The high transistor density afforded by modern VLSI processes have enabled the design of embedded processors that use clustered execution units to deliver high levels of performan...
Binu K. Mathew, Al Davis
137
Voted
CASES
2004
ACM
15 years 7 months ago
A low power architecture for embedded perception
Recognizing speech, gestures, and visual features are important interface capabilities for future embedded mobile systems. Unfortunately, the real-time performance requirements of...
Binu K. Mathew, Al Davis, Michael Parker