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» Design techniques for low-power systems
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DAC
2008
ACM
16 years 2 months ago
A power and temperature aware DRAM architecture
Technological advances enable modern processors to utilize increasingly larger DRAMs with rising access frequencies. This is leading to high power consumption and operating temper...
Song Liu, Seda Ogrenci Memik, Yu Zhang, Gokhan Mem...
PPL
2008
185views more  PPL 2008»
15 years 1 months ago
On Design and Application Mapping of a Network-on-Chip(NoC) Architecture
As the number of integrated IP cores in the current System-on-Chips (SoCs) keeps increasing, communication requirements among cores can not be sufficiently satisfied using either ...
Jun Ho Bahn, Seung Eun Lee, Yoon Seok Yang, Jungso...
ICCD
2007
IEEE
157views Hardware» more  ICCD 2007»
15 years 10 months ago
Limits on voltage scaling for caches utilizing fault tolerant techniques
This paper proposes a new low power cache architecture that utilizes fault tolerance to allow aggressively reduced voltage levels. The fault tolerant overhead circuits consume lit...
Mohammad A. Makhzan, Amin Khajeh Djahromi, Ahmed M...
ISVLSI
2008
IEEE
173views VLSI» more  ISVLSI 2008»
15 years 8 months ago
Hermes-GLP: A GALS Network on Chip Router with Power Control Techniques
The evolution of deep submicron technologies allows the development of increasingly complex Systems on a Chip (SoC). However, this evolution is rendering less viable some well-est...
Julian J. H. Pontes, Matheus T. Moreira, Rafael So...
ISLPED
1999
ACM
129views Hardware» more  ISLPED 1999»
15 years 6 months ago
Power scalable processing using distributed arithmetic
A recent trend in low power design has been the employment of reduced precision processing methods for decreasing arithmetic activity and average power dissipation. Such designs c...
Rajeevan Amirtharajah, Thucydides Xanthopoulos, An...