5672 search results - page 6 / 1135 » Design techniques for low-power systems |
88
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DAC
2005
ACM
15 years 1 months ago
2005
ACM
This paper proposes a low power technique, called SBR (Sign Bit Reduction) which may reduce the switching activity in multipliers as well as data buses. Utilizing the multipliers ...
109
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CASES
2006
ACM
15 years 5 months ago
2006
ACM
We propose an architecture that uses NAND flash memory to reduce main memory power in web server platforms. Our architecture uses a two level file buffer cache composed of a re...
VLSID
2006
IEEE
16 years 18 hour ago
2006
IEEE
This article describes a standard cell based novel implementation of a low-power Viterbi Decoder (VD) targeted for the IEEE 802.11a Wireless LAN system. Multiple clock rates have ...
ISLPED
1995
ACM
15 years 3 months ago
1995
ACM
The high-frequency oscillator is one of the major causes of both high power consumption and high ElectroMagnetic Interference (EMI) in Embedded Systems (ES). This paper presents a...
GLOBECOM
2007
IEEE
15 years 1 months ago
2007
IEEE
: The improvement of spectral efficiency comes at the cost of exponential increment of signal processing complexity [1]. Hence, the energy-efficiency of baseband has recently turne...