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PATMOS
2004
Springer
15 years 5 months ago
A Dual Low Power and Crosstalk Immune Encoding Scheme for System-on-Chip Buses
Abstract. Crosstalk causes logical errors due to data dependent delay degradation as well as energy consumption and is considered the biggest signal integrity challenge for long on...
Zahid Khan, Tughrul Arslan, Ahmet T. Erdogan
ANNPR
2006
Springer
15 years 1 months ago
A Convolutional Neural Network Tolerant of Synaptic Faults for Low-Power Analog Hardware
Abstract. Recently, the authors described a training method for a convolutional neural network of threshold neurons. Hidden layers are trained by by clustering, in a feed-forward m...
Johannes Fieres, Karlheinz Meier, Johannes Schemme...
LCTRTS
2007
Springer
15 years 5 months ago
Compiler-managed partitioned data caches for low power
Set-associative caches are traditionally managed using hardwarebased lookup and replacement schemes that have high energy overheads. Ideally, the caching strategy should be tailor...
Rajiv A. Ravindran, Michael L. Chu, Scott A. Mahlk...
ISLPED
1998
ACM
102views Hardware» more  ISLPED 1998»
15 years 3 months ago
Low power methodology and design techniques for processor design
J. Patrick Brennan, Alvar Dean, Stephan Kenyon, Se...
ISQED
2010
IEEE
170views Hardware» more  ISQED 2010»
15 years 1 months ago
New SRAM design using body bias technique for ultra low power applications
A new SRAM design is proposed. Body biasing improves the static noise margin (SNM) improved by at least 15% compared to the standard cells. Through using this technique, lowering ...
Farshad Moradi, Dag T. Wisland, Hamid Mahmoodi, Yn...