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» Design verification via simulation and automatic test patter...
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99
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TVLSI
2008
140views more  TVLSI 2008»
14 years 9 months ago
A Novel Mutation-Based Validation Paradigm for High-Level Hardware Descriptions
We present a Mutation-based Validation Paradigm (MVP) technology that can handle complete high-level microprocessor implementations and is based on explicit design error modeling, ...
Jorge Campos, Hussain Al-Asaad
113
Voted
HASE
2008
IEEE
14 years 9 months ago
Aiding Modular Design and Verification of Safety-Critical Time-Triggered Systems by Use of Executable Formal Specifications
Designing safety-critical systems is a complex process, and especially when the design is carried out at different f abstraction where the correctness of the design at one level i...
Kohei Sakurai, Péter Bokor, Neeraj Suri
WWW
2002
ACM
15 years 10 months ago
Simulation, verification and automated composition of web services
Web services -- Web-accessible programs and devices ? are a key application area for the Semantic Web. With the proliferation of Web services and the evolution towards the Semanti...
Srini Narayanan, Sheila A. McIlraith
IOLTS
2008
IEEE
117views Hardware» more  IOLTS 2008»
15 years 3 months ago
Verification and Analysis of Self-Checking Properties through ATPG
Present and future semiconductor technologies are characterized by increasing parameters variations as well as an increasing susceptibility to external disturbances. Transient err...
Marc Hunger, Sybille Hellebrand
ASPDAC
2004
ACM
94views Hardware» more  ASPDAC 2004»
15 years 1 months ago
Improving simulation-based verification by means of formal methods
The design of complex systems is largely ruled by the time needed for verification. Even though formal methods can provide higher reliability, in practice often simulation based ve...
Görschwin Fey, Rolf Drechsler