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ICCD
2004
IEEE
103views Hardware» more  ICCD 2004»
14 years 3 months ago
Design-Space Exploration of Power-Aware On/Off Interconnection Networks
— With power a major limiting factor in the design of scalable interconnected systems, power-aware networks will become inherent components of single-chip and multi-chip systems....
Vassos Soteriou, Li-Shiuan Peh
HPCA
2005
IEEE
13 years 12 months ago
Exploring the Design Space of Power-Aware Opto-Electronic Networked Systems
As microprocessors become increasingly interconnected, the power consumed by the interconnection network can no longer be ignored. Moreover, with demand for link bandwidth increas...
Xuning Chen, Li-Shiuan Peh, Gu-Yeon Wei, Yue-Kai H...
HPCC
2007
Springer
13 years 10 months ago
Power-Aware Fat-Tree Networks Using On/Off Links
Abstract. Nowadays, power consumption reduction techniques are being increasingly used in computer systems, and high-performance computing systems are not an exception. In particul...
Marina Alonso, Salvador Coll, Vicente Santonja, Ju...
ICCAD
2003
IEEE
144views Hardware» more  ICCAD 2003»
14 years 3 months ago
A High-level Interconnect Power Model for Design Space Exploration
— In this paper, we present a high-level power model to estimate the power consumption in semi-global and global interconnects. Such interconnects are used for communications bet...
Pallav Gupta, Lin Zhong, Niraj K. Jha
IPPS
2006
IEEE
14 years 8 days ago
Exploring the design space of an optimized compiler approach for mesh-like coarse-grained reconfigurable architectures
In this paper we study the performance improvements and trade-offs derived from an optimized mapping approach applied on a parametric coarse grained reconfigurable array architect...
Grigoris Dimitroulakos, Michalis D. Galanis, Const...