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134
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HPCA
2006
IEEE
16 years 3 months ago
Completely verifying memory consistency of test program executions
An important means of validating the design of commercial-grade shared memory multiprocessors is to run a large number of pseudo-random test programs on them. However, when intent...
Chaiyasit Manovit, Sudheendra Hangal
142
Voted
IJAMC
2010
134views more  IJAMC 2010»
15 years 1 months ago
HyperVerse: simulation and testbed reconciled
—When dealing with dynamic large-scale topologies such as those underlying peer-to-peer (P2P) distributed virtual environments (DVE), one inescapably reaches the point where eith...
Jean Botev, Markus Esch, Hermann Schloss, Ingo Sch...
HPCA
2011
IEEE
14 years 7 months ago
HAQu: Hardware-accelerated queueing for fine-grained threading on a chip multiprocessor
Queues are commonly used in multithreaded programs for synchronization and communication. However, because software queues tend to be too expensive to support finegrained paralle...
Sanghoon Lee, Devesh Tiwari, Yan Solihin, James Tu...
EUROPAR
2009
Springer
15 years 7 months ago
StarPU: A Unified Platform for Task Scheduling on Heterogeneous Multicore Architectures
Abstract. In the field of HPC, the current hardware trend is to design multiprocessor architectures that feature heterogeneous technologies such as specialized coprocessors (e.g., ...
Cédric Augonnet, Samuel Thibault, Raymond N...
HPDC
2010
IEEE
15 years 4 months ago
Scalability of communicators and groups in MPI
As the number of cores inside compute clusters continues to grow, the scalability of MPI (Message Passing Interface) is important to ensure that programs can continue to execute o...
Humaira Kamal, Seyed M. Mirtaheri, Alan Wagner
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