Sciweavers

5866 search results - page 268 / 1174
» Designing Accelerator-Based Distributed Systems for High Per...
Sort
View
EUROPAR
2008
Springer
15 years 6 months ago
Performance Implications of Cache Affinity on Multicore Processors
Cache affinity between a process and a processor is observed when the processor cache has accumulated some amount of the process state, i.e., data or instructions. Cache affinity i...
Vahid Kazempour, Alexandra Fedorova, Pouya Alagheb...
SIGCOMM
2012
ACM
13 years 6 months ago
Distributed content storage for just-in-time streaming
We propose a content distribution strategy over municipal WiFi networks where Access Points (APs) collaboratively cache popular multimedia content, and disseminate them in a manne...
Sourav Kumar Dandapat, Sanyam Jain, Romit Roy Chou...
GLVLSI
2010
IEEE
164views VLSI» more  GLVLSI 2010»
15 years 9 months ago
Performance and energy trade-offs analysis of L2 on-chip cache architectures for embedded MPSoCs
On-chip memory organization is one of the most important aspects that can influence the overall system behavior in multiprocessor systems. Following the trend set by high-perform...
Mohamed M. Sabry, Martino Ruggiero, Pablo Garcia D...
SPDP
1991
IEEE
15 years 7 months ago
Local vs. global memory in the IBM RP3: experiments and performance modelling
A number of experiments regarding the placement of instructions, private data and shared data in the Non-Uniform-Memory-Access multiprocessor, RP3 has been performed. Three Scient...
Mats Brorsson
IPPS
2009
IEEE
15 years 11 months ago
MGST: A framework for performance evaluation of Desktop Grids
Desktop Grids are rapidly gaining popularity as a costeffective computing platform for the execution of applications with extensive computing needs. As opposed to grids and cluste...
Majd Kokaly, Issam Al-Azzoni, Douglas G. Down