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HPCA
2009
IEEE
16 years 5 months ago
Dacota: Post-silicon validation of the memory subsystem in multi-core designs
The number of functional errors escaping design verification and being released into final silicon is growing, due to the increasing complexity and shrinking production schedules ...
Andrew DeOrio, Ilya Wagner, Valeria Bertacco
MICRO
2009
IEEE
148views Hardware» more  MICRO 2009»
15 years 11 months ago
Flip-N-Write: a simple deterministic technique to improve PRAM write performance, energy and endurance
The phase-change random access memory (PRAM) technology is fast maturing to production levels. Main advantages of PRAM are non-volatility, byte addressability, in-place programmab...
Sangyeun Cho, Hyunjin Lee
GECCO
2006
Springer
137views Optimization» more  GECCO 2006»
15 years 8 months ago
A method for parameter calibration and relevance estimation in evolutionary algorithms
We present and evaluate a method for estimating the relevance and calibrating the values of parameters of an evolutionary algorithm. The method provides an information theoretic m...
Volker Nannen, A. E. Eiben
128
Voted
CSREASAM
2006
15 years 6 months ago
Using Aspects and Compilation Techniques to Dynamically Manage Applications
- The emergence of middleware solutions and new services even on small devices will need adapted distributed management solutions which address these specificities, both in terms o...
Bernard Kaddour, Joël Quinqueton
EUROPAR
2003
Springer
15 years 10 months ago
Obtaining Hardware Performance Metrics for the BlueGene/L Supercomputer
Hardware performance monitoring is the basis of modern performance analysis tools for application optimization. We are interested in providing such performance analysis tools for t...
Pedro Mindlin, José R. Brunheroto, Luiz De ...