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ISCA
2008
IEEE
188views Hardware» more  ISCA 2008»
16 years 21 days ago
MIRA: A Multi-layered On-Chip Interconnect Router Architecture
Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron tech...
Dongkook Park, Soumya Eachempati, Reetuparna Das, ...
NETGAMES
2006
ACM
16 years 8 days ago
On the support for heterogeneity in networked virtual environment
This paper presents our ongoing research activity to design and implement a framework for an networked virtual environment (NVE) that efficiently supports both hardware and softwa...
Hiroshi Fujinoki
MICRO
2010
IEEE
189views Hardware» more  MICRO 2010»
15 years 4 months ago
A Dynamically Adaptable Hardware Transactional Memory
Most Hardware Transactional Memory (HTM) implementations choose fixed version and conflict management policies at design time. While eager HTM systems store transactional state in-...
Marc Lupon, Grigorios Magklis, Antonio Gonzá...
P2P
2010
IEEE
127views Communications» more  P2P 2010»
15 years 4 months ago
Waiting for Anonymity: Understanding Delays in the Tor Overlay
Although Tor is the most widely used overlay for providing anonymity services, its users often experience very high delays. Because much of Tor usage is for Web applications, which...
Prithula Dhungel, Moritz Steiner, Ivinko Rimac, Vo...
JSA
2006
81views more  JSA 2006»
15 years 6 months ago
Deferred locking with shadow transaction for client-server DBMSs
Data-shipping systems that allow inter-transaction caching raise the need of a transactional cache consistency maintenance (CCM) protocol because each client is able to cache a po...
Hyeokmin Kwon, Songchun Moon