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SI3D
1995
ACM
15 years 6 months ago
The Sort-First Rendering Architecture for High-Performance Graphics
Interactive graphics applications have long been challenging graphics system designers by demanding machines that can provide ever increasing polygon rendering performance. Anothe...
Carl Mueller
PACS
2000
Springer
99views Hardware» more  PACS 2000»
15 years 6 months ago
Dynamically Reconfiguring Processor Resources to Reduce Power Consumption in High-Performance Processors
Power dissipation is a major concern not only for portable systems, but also for high-performance systems. In the past, energy consumption and processor heating was reduced mainly...
Roberto Maro, Yu Bai, R. Iris Bahar
126
Voted
ASPLOS
2000
ACM
15 years 7 months ago
Evaluating Design Alternatives for Reliable Communication on High-Speed Networks
We systematically evaluate the performance of five implementations of a single, user-level communication interface. Each implementation makes different architectural assumptions ...
Raoul Bhoedjang, Kees Verstoep, Tim Rühl, Hen...
ICEIS
2003
IEEE
15 years 8 months ago
Distributed Overload Control for Real-Time Replicated Database Systems
: In order to meet their temporal constraints, current applications such as Web-based services and electronic commerce use the technique of data replication. To take the replicatio...
Samia Saad-Bouzefrane, Claude Kaiser
TVLSI
2008
164views more  TVLSI 2008»
15 years 2 months ago
Dynamically Configurable Bus Topologies for High-Performance On-Chip Communication
The on-chip communication architecture is a major determinant of overall performance in complex System-on-Chip (SoC) designs. Since the communication requirements of SoC components...
Krishna Sekar, Kanishka Lahiri, Anand Raghunathan,...