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ISQED
2007
IEEE
162views Hardware» more  ISQED 2007»
15 years 9 months ago
Balanced Scheduling and Operation Chaining in High-Level Synthesis for FPGA Designs
In high-level synthesis for FPGA designs, scheduling and chaining of operations for optimal performance remain challenging problems. In this paper, we present a balanced schedulin...
David Zaretsky, Gaurav Mittal, Robert P. Dick, Pri...
SIGMOD
2008
ACM
126views Database» more  SIGMOD 2008»
16 years 3 months ago
On efficient top-k query processing in highly distributed environments
Lately the advances in centralized database management systems show a trend towards supporting rank-aware query operators, like top-k, that enable users to retrieve only the most ...
Akrivi Vlachou, Christos Doulkeridis, Kjetil N&osl...
DAC
2011
ACM
14 years 2 months ago
DRAIN: distributed recovery architecture for inaccessible nodes in multi-core chips
As transistor dimensions continue to scale deep into the nanometer regime, silicon reliability is becoming a chief concern. At the same time, transistor counts are scaling up, ena...
Andrew DeOrio, Konstantinos Aisopos, Valeria Berta...
HPCS
2002
IEEE
15 years 8 months ago
CoStore: A Reliable and Highly Available Storage System Using Clusters
The CoStore cluster architecture has been proposed to construct a reliable and highly available storage system. A prototype CoStore has been implemented and its performance has be...
Yong Chen, Lionel M. Ni, Cheng-Zhong Xu, Mingyao Y...
HPCA
2003
IEEE
16 years 3 months ago
Control Techniques to Eliminate Voltage Emergencies in High Performance Processors
Increasing focus on power dissipation issues in current microprocessors has led to a host of proposals for clock gating and other power-saving techniques. While generally effectiv...
Russ Joseph, David Brooks, Margaret Martonosi