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GLOBECOM
2006
IEEE
15 years 9 months ago
Improved High-rate Space-Time-Frequency Block Codes
— High-rate space-time-frequency block codes (STFBC) are promising for achieving high bandwidth efficiency, low overhead and latency. Recently, a class of low-complexity STFBC m...
Jinsong Wu, Steven D. Blostein
153
Voted
FPGA
2004
ACM
158views FPGA» more  FPGA 2004»
15 years 9 months ago
A novel coarse-grain reconfigurable data-path for accelerating DSP kernels
In this paper, an efficient implementation of a high performance coarse-grain reconfigurable data-path on a mixed-granularity reconfigurable platform is presented. It consists of ...
Michalis D. Galanis, George Theodoridis, Spyros Tr...
106
Voted
SLIP
2003
ACM
15 years 8 months ago
A hierarchical three-way interconnect architecture for hexagonal processors
The problem of interconnect architecture arises when an array of processors needs to be integrated on one chip. With the deep sub-micron technology, devices become cheap while wir...
Feng Zhou, Esther Y. Cheng, Bo Yao, Chung-Kuan Che...
120
Voted
INFOCOM
1999
IEEE
15 years 7 months ago
Periodic Broadcasting with VBR-Encoded Video
We consider designing near video on demand (VoD) systems that minimize start-up latency while maintaining high image quality. Recently several research teams have developed period...
Despina Saparilla, Keith W. Ross, Martin Reisslein
MICRO
1997
IEEE
82views Hardware» more  MICRO 1997»
15 years 7 months ago
Procedure Based Program Compression
Cost and power consumption are two of the most important design factors for many embedded systems, particularly consumer devices. Products such as Personal Digital Assistants, pag...
Darko Kirovski, Johnson Kin, William H. Mangione-S...