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ESANN
2006
14 years 11 months ago
Spatial filters for the classification of event-related potentials
Spatial filtering is a widely used dimension reduction method in electroencephalogram based brain-computer interface systems. In this paper a new algorithm is proposed, which learn...
Ulrich Hoffmann, Jean-Marc Vesin, Touradj Ebrahimi
NIPS
2000
14 years 11 months ago
Foundations for a Circuit Complexity Theory of Sensory Processing
We introduce total wire length as salient complexity measure for an analysis of the circuit complexity of sensory processing in biological neural systems and neuromorphic engineer...
Robert A. Legenstein, Wolfgang Maass
ASPDAC
2004
ACM
109views Hardware» more  ASPDAC 2004»
15 years 3 months ago
Resource-constrained low-power bus encoding with crosstalk delay elimination
— In deep-submicron (DSM) technology, minimizing power consumption of a bus is one of the most important design objectives in embedded system-on-chip (SoC) design. In this paper,...
Meeyoung Cha, Chun-Gi Lyuh, Taewhan Kim
85
Voted
DATE
2008
IEEE
145views Hardware» more  DATE 2008»
15 years 4 months ago
Minimizing Virtual Channel Buffer for Routers in On-chip Communication Architectures
We present a novel methodology for design space exploration using a two-steps scheme to optimize the number of virtual channel buffers (buffers take the premier share of the route...
Mohammad Abdullah Al Faruque, Jörg Henkel
ICCD
1997
IEEE
90views Hardware» more  ICCD 1997»
15 years 1 months ago
TITAC-2: An asynchronous 32-bit microprocessor based on Scalable-Delay-Insensitive model
Asynchronous design has a potential of solving many difficulties, such as clock skew and power consumption, which synchronous counterpart suffers with current and future VLSI tech...
Akihiro Takamura, Masashi Kuwako, Masashi Imai, Ta...