Sciweavers

1155 search results - page 92 / 231
» Designing Benchmarks for P2P Systems
Sort
View
CODES
1999
IEEE
15 years 8 months ago
An ASIP design methodology for embedded systems
A well-known challenge during processor design is to obtain the best possible results for a typical target application domain that is generally described as a set of benchmarks. O...
Kayhan Küçükçakar
CASES
2008
ACM
15 years 6 months ago
Design space exploration for field programmable compressor trees
The Field Programmable Compressor Tree (FPCT) is a programmable compressor tree (e.g., a Wallace or Dadda Tree) intended for integration in an FPGA or other reconfigurable device....
Seyed Hosein Attarzadeh Niaki, Alessandro Cevrero,...
IPPS
2005
IEEE
15 years 9 months ago
Experiences with Soft-Core Processor Design
Soft-core processors exploit the flexibility of Field Programmable Gate Arrays (FPGAs) to allow a system designer to customize the processor to the needs of a target application....
Franjo Plavec, Blair Fort, Zvonko G. Vranesic, Ste...
DAC
2008
ACM
16 years 5 months ago
Partial order reduction for scalable testing of systemC TLM designs
A SystemC simulation kernel consists of a deterministic implementation of the scheduler, whose specification is nondeterministic. To leverage testing of a SystemC TLM design, we f...
Sudipta Kundu, Malay K. Ganai, Rajesh Gupta
DFT
2005
IEEE
110views VLSI» more  DFT 2005»
15 years 9 months ago
A design flow for protecting FPGA-based systems against single event upsets
SRAM-based Field Programmable Gate Arrays (FPGAs) are very susceptible to Single Event Upsets (SEUs) that may have dramatic effects on the circuits they implement. In this paper w...
Luca Sterpone, Massimo Violante