7778 search results - page 1164 / 1556 » Designing Controllers for Reachability |
165
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LCTRTS
2007
Springer
15 years 11 months ago
2007
Springer
Set-associative caches are traditionally managed using hardwarebased lookup and replacement schemes that have high energy overheads. Ideally, the caching strategy should be tailor...
127
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HPCS
2006
IEEE
15 years 11 months ago
2006
IEEE
This paper presents the initial design of the Cyclops-64 (C64) system software infrastructure and tools under development as a joint effort between IBM T.J. Watson Research Center...
134
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IEEEPACT
2006
IEEE
15 years 11 months ago
2006
IEEE
The address sequence on the processor-memory bus can reveal abundant information about the control flow of a program. This can lead to critical information leakage such as encryp...
124
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INFOCOM
2006
IEEE
15 years 11 months ago
2006
IEEE
—Routing algorithms such as Distance Vector and Link States have the routing table size as ΩΩΩΩ (n), where n is the number of destination identifiers, thus providing only...
165
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RTSS
2006
IEEE
15 years 11 months ago
2006
IEEE
Modern FPGA devices, which include (multiple) processor core(s) as diffused IP on the silicon die, provide an excellent platform for developing custom multiprocessor systems-on-pr...