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DAC
1995
ACM
15 years 7 months ago
On the Bounded-Skew Clock and Steiner Routing Problems
We study the minimum-costbounded-skewrouting tree (BST) problem under the linear delay model. This problem captures several engineering tradeoffs in the design of routing topologi...
Dennis J.-H. Huang, Andrew B. Kahng, Chung-Wen Alb...
ICCAD
1995
IEEE
94views Hardware» more  ICCAD 1995»
15 years 7 months ago
Test register insertion with minimum hardware cost
Implementing a built-in self-test by a "test per clock" scheme offers advantages concerning fault coverage, detection of delay faults, and test application time. Such a ...
Albrecht P. Stroele, Hans-Joachim Wunderlich
ISCAS
1995
IEEE
91views Hardware» more  ISCAS 1995»
15 years 7 months ago
An FPGA Based Reconfigurable Coprocessor Board Utilizing a Mathematics of Arrays
Abstract -- Work in progress at the University of Missouri-Rolla on hardware assists for high performance computing is presented. This research consists of a novel field programmab...
W. Eatherton, J. Kelly, T. Schiefelbein, H. Pottin...
SIGMOD
1997
ACM
113views Database» more  SIGMOD 1997»
15 years 7 months ago
Size Separation Spatial Join
The Partitioned Based Spatial-Merge Join (PBSM) of Patel and DeWitt and the Size Separation Spatial Join (S3 J) of Koudas and Sevcik are considered to be among the most efficient ...
Nick Koudas, Kenneth C. Sevcik
142
Voted
ICML
1994
IEEE
15 years 7 months ago
Efficient Algorithms for Minimizing Cross Validation Error
Model selection is important in many areas of supervised learning. Given a dataset and a set of models for predicting with that dataset, we must choose the model which is expected...
Andrew W. Moore, Mary S. Lee
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