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FDL
2007
IEEE
15 years 11 months ago
Automatic High Level Assertion Generation and Synthesis for Embedded System Design
SystemVerilog encapsulates both design description and verification properties in one language and provides a unified environment for engineers who have the formidable challenge o...
Lun Li, Frank P. Coyle, Mitchell A. Thornton
DAC
1994
ACM
15 years 8 months ago
Design Methodology Management Using Graph Grammars
In this paper, we present a design methodology management system, which assists designers in selecting a suitable design process and invoking the selected sequence of tools on the...
Reid A. Baldwin, Moon-Jung Chung
BCSHCI
2007
15 years 6 months ago
Interaction design in the wild
The StoryBank project in the UK is exploring the application of digital storytelling technology to information sharing in the developing world. A multidisciplinary team of interac...
Dorothy Rachovides, David Frohlich, Maxine Frank
DAC
2000
ACM
16 years 5 months ago
The role of custom design in ASIC Chips
Custom design, in which the designer controls the physical structure of the chip, can greatly improve the speed, power, and delay of an ASIC chip without affecting design time. Th...
William J. Dally, Andrew Chang
UML
2005
Springer
15 years 10 months ago
UML Model Mappings for Platform Independent User Interface Design
While model based design of platform independent application logic has already shown significant success, the design of platform independent user interfaces still needs further in...
Tim Schattkowsky, Marc Lohmann