397 search results - page 28 / 80 » Designing Fast Asynchronous Circuits |
122
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IPL
2011
14 years 4 months ago
2011
We propose a probabilistic network model, called asynchronous bounded expected delay (ABE), which requires a known bound on the expected message delay. In ABE networks all asynchr...
102
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ASPDAC
2010
ACM
14 years 11 months ago
2010
ACM
Asynchronous on-chip networks are power efficient and tolerant to process variation but they are slower than synchronous on-chip networks. A low latency asynchronous wormhole route...
116
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ET
2000
15 years 1 months ago
2000
The paper presents a novel hierarchical approach to test pattern generation for sequential circuits based on an input model of mixed-level decision diagrams. A method that handles,...
113
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HPCC
2007
Springer
15 years 7 months ago
2007
Springer
Abstract. Low-power design became crucial with the widespread use of the embedded systems, where a small battery has to last for a long period. The embedded processors need to efï¬...
102
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IFIP
1999
Springer
15 years 5 months ago
1999
Springer
We describe a new method for design error diagnosis in digital circuits, that doesn’t use any error model. A diagnostic specific pre-analysis of the circuit extracts a subcircui...