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OPODIS
2004
15 years 8 months ago
Lock-Free and Practical Doubly Linked List-Based Deques Using Single-Word Compare-and-Swap
Abstract. We present an efficient and practical lock-free implementation of a concurrent deque that supports parallelism for disjoint accesses and uses atomic primitives which are ...
Håkan Sundell, Philippas Tsigas
CASES
2003
ACM
16 years 1 days ago
Frequent loop detection using efficient non-intrusive on-chip hardware
Dynamic software optimization methods are becoming increasingly popular for improving software performance and power. The first step in dynamic optimization consists of detecting ...
Ann Gordon-Ross, Frank Vahid
ICCD
2006
IEEE
128views Hardware» more  ICCD 2006»
16 years 3 months ago
Polaris: A System-Level Roadmap for On-Chip Interconnection Networks
Technology trends are driving parallel on-chip architectures in the form of multi-processor systems-on-a-chip (MPSoCs) and chip multi-processors (CMPs). In these systems the incre...
Vassos Soteriou, Noel Eisley, Hangsheng Wang, Bin ...
IJCAT
2008
72views more  IJCAT 2008»
15 years 6 months ago
Capacity analysis of container terminals using simulation techniques
Modeling and simulation are essential tools for the design and analysis of container terminals. A computer model can emulate the activities at various levels of details and captur...
Shell-Ying Huang, Wen-Jing Hsu, Chuanyu Chen, Rong...
WISER
2004
ACM
16 years 6 days ago
Hardware/software co-design for power system test development
Many hardware/software co-design models have been proposed [7, 2, 5, 6] that attempt to address problems in the hardware/software interface, in partitioning the system between har...
Austin Armbruster, Matt Ryan, Xiaoqing Frank Liu, ...