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ASPLOS
1992
ACM
15 years 3 months ago
High Speed Switch Scheduling for Local Area Networks
Current technology trends make it possible to build communication networks that can support high performance distributed computing. This paper describes issues in the design of a ...
Thomas E. Anderson, Susan S. Owicki, James B. Saxe...
ICCCN
2008
IEEE
15 years 5 months ago
Logical Topology Design for IP-over-WDM Networks: A Hybrid Approach for Minimum Protection Capacity
—The problem of designing high capacity and high bit rate IP-over-WDM networks, which can provide uninterrupted service in the presence of network equipment failures, continues t...
Muhammad S. Javed, Krishnaiyan Thulasiraman, Guoli...
BMCBI
2008
103views more  BMCBI 2008»
14 years 11 months ago
Detection of protein catalytic residues at high precision using local network properties
Background: Identifying the active site of an enzyme is a crucial step in functional studies. While protein sequences and structures can be experimentally characterized, determini...
Patrick Slama, Ioannis Filippis, Michael Lappe
COR
2007
109views more  COR 2007»
14 years 11 months ago
Assessing performance and uncertainty in developing carpet reverse logistics systems
TheUScarpetindustryisstrivingtoreacha40%diversionratefromlandfillsby2012,accordingtoamemorandum of understanding signed by industry and government officials in 2002. As a result...
Markus Biehl, Edmund Prater, Matthew J. Realff
DATE
2002
IEEE
95views Hardware» more  DATE 2002»
15 years 4 months ago
Optimal Transistor Tapering for High-Speed CMOS Circuits
Transistor tapering is a widely used technique applied to optimize the geometries of CMOS transistors in highperformance circuit design with a view to minimizing the delay of a FE...
Li Ding 0002, Pinaki Mazumder