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HOTI
2005
IEEE
15 years 5 months ago
Hybrid Cache Architecture for High Speed Packet Processing
: The exposed memory hierarchies employed in many network processors (NPs) are expensive in terms of meeting the worst-case processing requirement. Moreover, it is difficult to ef...
Zhen Liu, Kai Zheng, Bin Liu
APPT
2003
Springer
15 years 4 months ago
A Highly Efficient FC-SAN Based on Load Stream
The speed of storing and fetching data on SCSI disks has a great restriction on the efficiency of SAN based on Fiber Channel Network. In this paper, a high-efficient FC-SAN storage...
Jiwu Shu, Jun Yao, Changdong Fu, Weimin Zheng
RECONFIG
2008
IEEE
225views VLSI» more  RECONFIG 2008»
15 years 5 months ago
A Hardware Filesystem Implementation for High-Speed Secondary Storage
Platform FPGAs are capable of hosting entire Linuxbased systems including standard peripherals, integrated network interface cards and even disk controllers on a single chip. File...
Ashwin A. Mendon, Ron Sass
TVLSI
2008
157views more  TVLSI 2008»
14 years 11 months ago
Scalable QoS-Aware Memory Controller for High-Bandwidth Packet Memory
This paper proposes a high-performance scalable quality-of-service (QoS)-aware memory controller for the packet memory where packet data are stored in network routers. A major chal...
Hyuk-Jun Lee, Eui-Young Chung
TC
2010
14 years 10 months ago
Design and Analysis of On-Chip Networks for Large-Scale Cache Systems
—Switched networks have been adopted in on-chip communication for their scalability and efficient resource sharing. However, using a general network for a specific domain may res...
Yuho Jin, Eun Jung Kim, Ki Hwan Yum