85 search results - page 14 / 17 » Designing Memory Subsystems Resilient to Process Variations |
104
Voted
PATMOS
2007
Springer
15 years 3 months ago
2007
Springer
—Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the...
TCAD
2008
14 years 9 months ago
2008
Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the mos...
ISCA
1995
IEEE
15 years 1 months ago
1995
IEEE
Accurate instruction fetch and branch prediction is increasingly important on today’s wide-issue architectures. Fetch prediction is the process of determining the next instructi...
MICRO
2007
IEEE
15 years 3 months ago
2007
IEEE
Aggressive technology scaling over the years has helped improve processor performance but has caused a reduction in processor reliability. Shrinking transistor sizes and lower sup...
ISQED
2009
IEEE
15 years 4 months ago
2009
IEEE
A system-level statistical analysis methodology is described that captures the impact of inter- and intra-die process variations for read timing failures in SRAM circuit blocks. U...