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CLUSTER
2007
IEEE
15 years 3 months ago
Identifying energy-efficient concurrency levels using machine learning
Abstract-- Multicore microprocessors have been largely motivated by the diminishing returns in performance and the increased power consumption of single-threaded ILP microprocessor...
Matthew Curtis-Maury, Karan Singh, Sally A. McKee,...
ISCAS
2005
IEEE
152views Hardware» more  ISCAS 2005»
15 years 4 months ago
Dictionary-based program compression on transport triggered architectures
— Program code size has become a critical design constraint of embedded systems. Large program codes require large memories, which increase the size and cost of the chip. Poor co...
Jari Heikkinen, Andrea G. M. Cilio, Jarmo Takala, ...
CODES
2004
IEEE
15 years 2 months ago
Design and programming of embedded multiprocessors: an interface-centric approach
We present design technology for the structured design and programming of embedded multi-processor systems. It comprises a task-level interface that can be used both for developin...
Pieter van der Wolf, Erwin A. de Kock, Tomas Henri...
PPOPP
2005
ACM
15 years 4 months ago
Revocable locks for non-blocking programming
In this paper we present a new form of revocable lock that streamlines the construction of higher level concurrency abstractions such as atomic multi-word heap updates. The key id...
Tim Harris, Keir Fraser
FPL
2006
Springer
242views Hardware» more  FPL 2006»
15 years 2 months ago
TMD-MPI: An MPI Implementation for Multiple Processors Across Multiple FPGAs
With current FPGAs, designers can now instantiate several embedded processors, memory units, and a wide variety of IP blocks to build a single-chip, high-performance multiprocesso...
Manuel Saldaña, Paul Chow