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CHES
2009
Springer
150views Cryptology» more  CHES 2009»
15 years 7 months ago
A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions
Power-based side channel attacks are a significant security risk, especially for embedded applications. To improve the security of such devices, protected logic styles have been p...
Francesco Regazzoni, Alessandro Cevrero, Fran&cced...
114
Voted
ICNP
2006
IEEE
15 years 6 months ago
Rigorous Protocol Design in Practice: An Optical Packet-Switch MAC in HOL
— This paper reports on an experiment in network protocol design: we use novel rigorous techniques in the design process of a new protocol, in a close collaboration between syste...
Adam Biltcliffe, Michael Dales, Sam Jansen, Tom Ri...
CODES
2000
IEEE
15 years 5 months ago
Towards a new standard for system-level design
—Huge new design challenges for system-on-chip (SoC) are the result of decreasing time-to-market coupled with rapidly increasing gate counts and embedded software representing 50...
Stan Y. Liao
IJRR
2008
186views more  IJRR 2008»
15 years 24 days ago
Automated Design of Adaptive Controllers for Modular Robots using Reinforcement Learning
Designing distributed controllers for self-reconfiguring modular robots has been consistently challenging. We have developed a reinforcement learning approach which can be used bo...
Paulina Varshavskaya, Leslie Pack Kaelbling, Danie...
GLVLSI
2009
IEEE
125views VLSI» more  GLVLSI 2009»
15 years 4 months ago
Spatial and temporal design debug using partial MaxSAT
Design debug remains one of the major bottlenecks in the VLSI design cycle today. Existing automated solutions strive to aid engineers in reducing the debug effort by identifying ...
Yibin Chen, Sean Safarpour, Andreas G. Veneris, Jo...