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IJIPM
2010
57views more  IJIPM 2010»
15 years 3 months ago
A Design and Simulation for Dynamically Reconfigurable Systolic Array
Toshiyuki Ishimura, Akinori Kanasugi
USS
2008
15 years 8 months ago
Experiment Isolation in a Secure Cluster Testbed
A major class of network emulation testbeds is based on the Utah Emulab design: a local cluster of experimental nodes interconnected through Ethernet switches using VLANs. The VLA...
Kevin Lahey, Robert Braden, Keith Sklower
JOCN
2010
70views more  JOCN 2010»
15 years 4 months ago
Optimizing Design Efficiency of Free Recall Events for fMRI
■ Free recall is a fundamental paradigm for studying memory retrieval in the context of minimal cue support. Accordingly, free recall has been extensively studied using behavior...
Ilke Öztekin, Nicole M. Long, David Badre
GLVLSI
2011
IEEE
344views VLSI» more  GLVLSI 2011»
14 years 10 months ago
Circuit design of a dual-versioning L1 data cache for optimistic concurrency
This paper proposes a novel L1 data cache design with dualversioning SRAM cells (dvSRAM) for chip multi-processors (CMP) that implement optimistic concurrency proposals. In this n...
Azam Seyedi, Adrià Armejach, Adrián ...