377 search results - page 11 / 76 » Designing a DHT for Low Latency and High Throughput |
DATE
2009
IEEE
15 years 4 months ago
2009
IEEE
—Packet-switched interconnect fabric is a promising on-chip communication solution for many-core architectures. It offers high throughput and excellent scalability for on-chip da...
DAC
2001
ACM
15 years 10 months ago
2001
ACM
This paper presents LOTTERYBUS, a novel high-performance communication architecture for system-on-chip (SoC) designs. The LOTTERYBUS architecture was designed to address the follo...
HPCA
2001
IEEE
15 years 10 months ago
2001
IEEE
In this papel; we address the severe performance gap caused by high processor clock rates and slow DRAM accesses. We show that even with an aggressive, next-generation memory syst...
98
Voted
INFOCOM
2010
IEEE
14 years 7 months ago
2010
IEEE
While scheduling the nodes in a wireless network to sleep periodically can save energy, it also incurs higher latency and lower throughput. We consider the problem of designing op...
CLUSTER
2009
IEEE
15 years 2 months ago
2009
IEEE
—Achieving high-performance message passing on top of generic ETHERNET hardware suffers from the NIC interruptdriven model where coalescing is usually involved. We present an in-...