377 search results - page 15 / 76 » Designing a DHT for Low Latency and High Throughput |
HIPEAC
2005
Springer
15 years 3 months ago
2005
Springer
Abstract. High end routers are targeted at providing worst case throughput guarantees over latency. Caches on the other hand are meant to help latency not throughput in a tradition...
IPPS
2010
IEEE
14 years 7 months ago
2010
IEEE
It is possible to implement the parallel random access machine (PRAM) on a chip multiprocessor (CMP) efficiently with an emulated shared memory (ESM) architecture to gain easy par...
67
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IROS
2009
IEEE
15 years 4 months ago
2009
IEEE
— In this paper the compliant low level control of a biologically inspired control architecture suited for bipedal dynamic walking robots is presented. It consists of elastic mec...
105
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PPL
2008
14 years 9 months ago
2008
As the number of integrated IP cores in the current System-on-Chips (SoCs) keeps increasing, communication requirements among cores can not be sufficiently satisfied using either ...
IPPS
2008
IEEE
15 years 4 months ago
2008
IEEE
Gossip-based Peer-to-Peer(P2P) streaming has been proved to be an effective and resilient method to stream qualified media contents in dynamic and heterogeneous network environme...