377 search results - page 16 / 76 » Designing a DHT for Low Latency and High Throughput |
DAC
2008
ACM
2008
ACM
An area-efficient high-throughput hybrid interconnection network for single-chip parallel processing
15 years 10 months ago
Single-chip parallel processing requires high bandwidth between processors and on-chip memory modules. A recently proposed Mesh-of-Trees (MoT) network provides high throughput and...
ISCA
1997
IEEE
15 years 1 months ago
1997
IEEE
In this paper we evaluate the performance of high bandwidth caches that employ multiple ports, multiple cycle hit times, on-chip DRAM, and a line buffer to find the organization t...
100
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LCN
2006
IEEE
15 years 3 months ago
2006
IEEE
Optical Burst Switching (OBS) is not only cost-effective, but also provides high throughput, high bandwidth utilization, and low transmission latency. These benefits render OBS a ...
ICWS
2009
IEEE
14 years 7 months ago
2009
IEEE
DHTs are scalable, self-organizing, and adaptive to underlying topology changes, thus being a promising infrastructure for realizing efficient Web service discovery. Range queries...
78
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ASPDAC
2009
ACM
15 years 4 months ago
2009
ACM
— To address the performance limitation brought by the scaling issues of on-chip global wires, a new configuration for global wiring using on-chip lossy transmission lines is pr...