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» Designing a DHT for Low Latency and High Throughput
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JNW
2006
86views more  JNW 2006»
14 years 9 months ago
Throughput and Delay Analysis of Unslotted IEEE 802.15.4
The IEEE 802.15.4 standard is designed as a low power and low data rate protocol offering high reliability. It defines a beaconed and unbeaconed version. In this work, we analyze t...
Benoît Latré, Pieter De Mil, Ingrid M...
INFOCOM
2012
IEEE
13 years 1 days ago
Maximizing throughput when achieving time fairness in multi-rate wireless LANs
Abstract—This paper focuses on designing a distributed medium access control algorithm that aims at achieving time fairness among contending stations and throughput maximization ...
Yuan Le, Liran Ma, Wei Cheng, Xiuzhen Cheng, Biao ...
ASPLOS
2004
ACM
15 years 3 months ago
Fingerprinting: bounding soft-error detection latency and bandwidth
Recent studies have suggested that the soft-error rate in microprocessor logic will become a reliability concern by 2010. This paper proposes an efficient error detection techniqu...
Jared C. Smolens, Brian T. Gold, Jangwoo Kim, Baba...
VLSID
2003
IEEE
78views VLSI» more  VLSID 2003»
15 years 10 months ago
Interface Design Techniques for Single-Chip Systems
This paper quantifies the performance of typical functional unit interface designs in single-chip systems. We introduce a specific equation to guide the design of optimal module i...
Robert H. Bell Jr., Lizy Kurian John
AHS
2006
IEEE
152views Hardware» more  AHS 2006»
15 years 3 months ago
Architecture of a Dynamically Reconfigurable NoC for Adaptive Reconfigurable MPSoC
This paper describes the architecture of our dynamically reconfigurable Network-on-Chip (NoC) architecture that has been proposed for reconfigurable Multiprocessor system-on-chip ...
Balal Ahmad, Ahmet T. Erdogan, Sami Khawam