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» Designing a DHT for Low Latency and High Throughput
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DAC
2005
ACM
15 years 10 months ago
Low power network processor design using clock gating
Abstract-- Network processors (NPs) have emerged as successful platforms to providing both high performance and flexibility in building powerful routers. Typical NPs incorporate mu...
Jia Yu, Jun Yang 0002, Laxmi N. Bhuyan, Yan Luo
HIPEAC
2007
Springer
15 years 3 months ago
A Throughput-Driven Task Creation and Mapping for Network Processors
Abstract. Network processors are programmable devices that can process packets at a high speed. A network processor is typified by multithreading and heterogeneous multiprocessing...
Lixia Liu, Xiao-Feng Li, Michael K. Chen, Roy Dz-C...
HPCA
2006
IEEE
15 years 10 months ago
A decoupled KILO-instruction processor
Building processors with large instruction windows has been proposed as a mechanism for overcoming the memory wall, but finding a feasible and implementable design has been an elu...
Miquel Pericàs, Adrián Cristal, Rube...
INFOCOM
2000
IEEE
15 years 2 months ago
Receiver Based Management of Low Bandwidth Access Links
Abstract—In this paper, we describe a receiver based congestion control policy that leverages TCP flow control mechanisms to prioritize mixed traffic loads across access links....
Neil T. Spring, Maureen Chesire, Mark Berryman, Vi...
ICASSP
2011
IEEE
14 years 1 months ago
User selection schemes for maximizing throughput of multiuser MIMO systems using Zero Forcing Beamforming
The performance of a multiuser MIMO broadcast system depends highly on how the users being served are selected from the pool of users requesting service. Though dirty paper coding...
Anh H. Nguyen, Bhaskar D. Rao