377 search results - page 22 / 76 » Designing a DHT for Low Latency and High Throughput |
ICASSP
2011
IEEE
14 years 1 months ago
2011
IEEE
This paper proposes an ultra low energy FFT processor suitable for sensor applications. The processor is based on R4MDC but achieves full utilization of computational elements. It...
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In this paper we study the design issues in improving TCP performance over the ATM UBR service. ATM-UBR switches respond to congestion by dropping cells when their buffers become f...
ISCA
2008
IEEE
15 years 4 months ago
2008
IEEE
Current state-of-the-art on-chip networks provide efficiency, high throughput, and low latency for one-to-one (unicast) traffic. The presence of one-to-many (multicast) or one-t...
MASCOTS
2007
2007
A Novel Flow Control Scheme for Best Effort Traffic in NoC Based on Source Rate Utility Maximization
14 years 11 months ago
—Advances in semiconductor technology, has enabled designers to put complex, massively parallel multiprocessor systems on a single chip. Network on Chip (NoC) that supports high ...
JSAC
2007
14 years 9 months ago
2007
— We provide a theoretical framework for cross-layer design in multimedia communications to optimize single-user throughput by selecting the transmitted bit rate and payload size...