377 search results - page 25 / 76 » Designing a DHT for Low Latency and High Throughput |
ASAP
2010
IEEE
14 years 11 months ago
2010
IEEE
In a traditional Network-on-Chip (NoC), latency and power dissipation increase with system size due to its inherent multi-hop communications. The performance of NoC communication ...
77
Voted
IPPS
2000
IEEE
15 years 2 months ago
2000
IEEE
This paper examines two Network Interface Card microarchitectures that support low latency, high bandwidth userlevel message passing in multi-user environments. The two are at dif...
CLUSTER
2002
IEEE
15 years 2 months ago
2002
IEEE
While a number of User-Level Protocols have been developed to reduce the gap between the performance capabilities of the physical network and the performance actually available, a...
88
Voted
DAC
2004
ACM
15 years 10 months ago
2004
ACM
As across-chip interconnect delays can exceed a clock cycle, wire pipelining becomes essential in high performance designs. Although it allows higher clock frequencies, it may cha...
FCCM
2006
IEEE
15 years 3 months ago
2006
IEEE
— Dedicated, spatially configured FPGA interconnect is efficient for applications that require high throughput connections between processing elements (PEs) but with a limited ...