377 search results - page 26 / 76 » Designing a DHT for Low Latency and High Throughput |
MICRO
2009
IEEE
15 years 6 months ago
2009
IEEE
On-chip networks are critical to the scaling of future multicore processors. The challenge for on-chip network is to reduce the cost including power consumption and area while pro...
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PC
2007
14 years 11 months ago
2007
The Sony–Toshiba–IBM Cell Broadband Engine (Cell/B.E.) is a heterogeneous multicore architecture that consists of a traditional microprocessor (PPE) with eight SIMD co-process...
DATE
2000
IEEE
15 years 4 months ago
2000
IEEE
In this paper we address the problem of designing very high throughput finite state machines (FSMs). The presence of loops in sequential circuits prevents a straightforward and g...
ISCAS
2006
IEEE
15 years 5 months ago
2006
IEEE
— By implementing an FPGA-based simulator, we investigate the performance of high-rate quasi-cyclic (QC) LDPC codes for the magnetic recording channel at very low sector error ra...
NOCS
2007
IEEE
15 years 6 months ago
2007
IEEE
Recent remarkable advances in nanoscale siliconphotonic integrated circuitry specifically compatible with CMOS fabrication have generated new opportunities for leveraging the uni...