377 search results - page 27 / 76 » Designing a DHT for Low Latency and High Throughput |
CF
2005
ACM
14 years 11 months ago
2005
ACM
In modern superscalar processors, the complex instruction scheduler could form the critical path of the pipeline stages and limit the clock cycle time. In addition, complex schedu...
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CF
2006
ACM
15 years 3 months ago
2006
ACM
Packet processing systems maintain high throughput despite relatively high memory latencies by exploiting the coarse-grained parallelism available between packets. In particular, ...
FCCM
2004
IEEE
15 years 1 months ago
2004
IEEE
We describe a flexible hardware encoder for regular and irregular low-density parity-check (LDPC) codes. Although LDPC codes achieve achieve better performance and lower decoding ...
SC
2009
ACM
15 years 4 months ago
2009
ACM
A stock market data processing system that can handle high data volumes at low latencies is critical to market makers. Such systems play a critical role in algorithmic trading, ri...
HPCA
2009
IEEE
15 years 10 months ago
2009
IEEE
Interconnection plays an important role in performance and power of CMP designs using deep sub-micron technology. The network-on-chip (NoCs) has been proposed as a scalable and hi...