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» Designing a DHT for Low Latency and High Throughput
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ITIIS
2008
158views more  ITIIS 2008»
14 years 9 months ago
Cross-layer Optimized Vertical Handover Schemes between Mobile WiMAX and 3G Networks
Nowadays, wireless packet data services are provided over Wireless MAN (WMAN) at a high data service rate, while 3G cellular networks provide wide-area coverage at a low data serv...
Jaeho Jo, Jinsung Cho
TVLSI
2008
157views more  TVLSI 2008»
14 years 9 months ago
Scalable QoS-Aware Memory Controller for High-Bandwidth Packet Memory
This paper proposes a high-performance scalable quality-of-service (QoS)-aware memory controller for the packet memory where packet data are stored in network routers. A major chal...
Hyuk-Jun Lee, Eui-Young Chung
TSP
2008
158views more  TSP 2008»
14 years 9 months ago
High-Speed VLSI Implementation of 2-D Discrete Wavelet Transform
This paper presents a systematic high-speed VLSI implementation of the discrete wavelet transform (DWT) based on hardware-efficient parallel FIR filter structures. High-speed 2-D D...
Chao Cheng, Keshab K. Parhi
FPL
2008
Springer
116views Hardware» more  FPL 2008»
14 years 11 months ago
NOC architecture design for multi-cluster chips
For the next generation of multi-core processors, the onchip interconnection networks must be efficient to achieve high data throughput and performance. Moreover, these interconne...
Henrique C. Freitas, Philippe Olivier Alexandre Na...
ICIP
2004
IEEE
15 years 11 months ago
A parallel mediated reality platform
Realtime image processing provides a general framework for robust mediated reality problems. This paper presents a realtime mediated reality system that is built upon realtime ima...
Rosco Hill, James Fung, Steve Mann