377 search results - page 32 / 76 » Designing a DHT for Low Latency and High Throughput |
80
Voted
GLOBECOM
2006
IEEE
15 years 3 months ago
2006
IEEE
Abstract−Several high performance LDPC codes have paritycheck matrices composed of permutation submatrices. We design a parallel-serial architecture to map the decoder of any str...
JSAC
2011
14 years 4 months ago
2011
—Due to the potential of enhancing traffic safety, protecting environment, and enabling new applications, vehicular communications, especially vehicle-to-vehicle (V2V) communica...
ISCAS
2005
IEEE
15 years 3 months ago
2005
IEEE
— We propose a new crossbar switch structure with adaptive bandwidth control. In a complex SoC design, the proposed crossbar switch efficiently incorporates various IPs with diff...
ANCS
2009
ACM
14 years 7 months ago
2009
ACM
Deterministic Finite Automaton (DFA) is well-known for its constant matching speed in worst case, and widely used in multistring matching, which is a critical technique in high pe...
VLSISP
2010
14 years 8 months ago
2010
A Split decoding algorithm is proposed which divides each row of the parity check matrix into two or multiple nearly-independent simplified partitions. The proposed method signific...