377 search results - page 34 / 76 » Designing a DHT for Low Latency and High Throughput |
101
click to vote
MICRO
2008
IEEE
15 years 4 months ago
2008
IEEE
As companies move towards many-core chips, an efficient onchip communication fabric to connect these cores assumes critical importance. To address limitations to wire delay scala...
SIGCOMM
2009
ACM
15 years 4 months ago
2009
ACM
New protocols for the data link and network layer are being proposed to address limitations of current protocols in terms of scalability, security, and manageability. High-speed r...
111
click to vote
COMCOM
2007
14 years 9 months ago
2007
Internet-based mobile ad hoc network (IMANET) combines a mobile ad hoc network (MANET) and the Internet to provide universal information accessibility. Although caching frequently...
167
click to vote
ISCA
2011
IEEE
14 years 1 months ago
2011
IEEE
Emerging memory technologies such as STT-RAM, PCRAM, and resistive RAM are being explored as potential replacements to existing on-chip caches or main memories for future multi-co...
SAMOS
2005
Springer
15 years 3 months ago
2005
Springer
This paper presents a new tool for the automatic generation of highly parallelized Finite Impulse Response (FIR) filters. In this approach we follow our PARO design methodology. P...