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» Designing a DHT for Low Latency and High Throughput
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DATE
2010
IEEE
158views Hardware» more  DATE 2010»
15 years 2 months ago
Energy- and endurance-aware design of phase change memory caches
—Phase change memory (PCM) is one of the most promising technology among emerging non-volatile random access memory technologies. Implementing a cache memory using PCM provides m...
Yongsoo Joo, Dimin Niu, Xiangyu Dong, Guangyu Sun,...
DSD
2008
IEEE
187views Hardware» more  DSD 2008»
15 years 4 months ago
How to Live with Uncertainties: Exploiting the Performance Benefits of Self-Timed Logic In Synchronous Design
Ultra low power digital systems are key for any future wireless sensor nodes but also inside nomadic embedded systems (such as inside the digital front end of software defined rad...
Giacomo Paci, A. Nackaerts, Francky Catthoor, Luca...
ASPLOS
1992
ACM
15 years 1 months ago
High Speed Switch Scheduling for Local Area Networks
Current technology trends make it possible to build communication networks that can support high performance distributed computing. This paper describes issues in the design of a ...
Thomas E. Anderson, Susan S. Owicki, James B. Saxe...
MOBISYS
2006
ACM
15 years 9 months ago
Measurement driven deployment of a two-tier urban mesh access network
Multihop wireless mesh networks can provide Internet access over a wide area with minimal infrastructure expenditure. In this work, we present a measurement driven deployment stra...
Joseph Camp, Joshua Robinson, Christopher Steger, ...
ICCD
2006
IEEE
137views Hardware» more  ICCD 2006»
15 years 6 months ago
Implementation and Evaluation of On-Chip Network Architectures
— Driven by the need for higher bandwidth and complexity reduction, off-chip interconnect has evolved from proprietary busses to networked architectures. A similar evolution is o...
Paul Gratz, Changkyu Kim, Robert G. McDonald, Step...