377 search results - page 38 / 76 » Designing a DHT for Low Latency and High Throughput |
ICASSP
2011
IEEE
14 years 1 months ago
2011
IEEE
For high-data-rate applications, turbo-like iterative decoders are implemented with parallel hardware architecture. However, to achieve high throughput, concurrent accesses to each...
ARITH
2009
IEEE
15 years 4 months ago
2009
IEEE
Moduli of the form 2n ± 1, which greatly simplify certain arithmetic operations in residue number systems (RNS), have been of longstanding interest. A steady stream of designs fo...
DATE
2008
IEEE
15 years 4 months ago
2008
IEEE
—The contribution of memory latency to execution time continues to increase, and latency hiding mechanisms become ever more important for efficient processor design. While high-...
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MOBICOM
2004
ACM
15 years 3 months ago
2004
ACM
In this paper we conduct a feasibility study of delay-critical safety applications over vehicular ad hoc networks based on the emerging dedicated short range communications (DSRC)...
CASES
2006
ACM
15 years 3 months ago
2006
ACM
The continuing miniaturization of technology coupled with wireless networks has made it feasible to physically embed sensor network systems into the environment. Sensor net proces...