377 search results - page 39 / 76 » Designing a DHT for Low Latency and High Throughput |
106
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SC
2009
ACM
15 years 4 months ago
2009
ACM
This paper presents a new distributed computing framework for Many Task Computing (MTC) applications, based on the Extensible Messaging and Presence Protocol (XMPP). A lightweight...
NOCS
2007
IEEE
15 years 4 months ago
2007
IEEE
We present a novel network-on-chip-based architecture for future programmable chips (FPGAs). A key challenge for FPGA design is supporting numerous highly variable design instance...
248
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DAC
2012
ACM
13 years 2 days ago
2012
ACM
Loop pipelining is a critical transformation in behavioral synthesis. It is crucial to producing hardware designs with acceptable latency and throughput. However, it is a complex ...
GCC
2003
Springer
15 years 2 months ago
2003
Springer
Due to their minimum consideration to an actual network topology, the existing peer-to-peer (P2P) overlay networks will lead to high latency and low efficiency. In TaChord, we pres...
VLSID
1993
IEEE
15 years 1 months ago
1993
IEEE
Low latency, application, specific multipliers are required for m,any DSP algorithms. Tree multipliers are an obvious answer to this requirement. However, tree architectures have ...