377 search results - page 41 / 76 » Designing a DHT for Low Latency and High Throughput |
FCCM
2002
IEEE
15 years 2 months ago
2002
IEEE
C-slow retiming (changing a design to support multiple instances of a computation) and datapath-aware placement have long been advocated by members of the FPGA synthesis community...
ACSAC
2006
IEEE
15 years 3 months ago
2006
IEEE
Comparing the system call sequence of a network application against a sandboxing policy is a popular approach to detecting control-hijacking attack, in which the attacker exploits...
86
Voted
IPPS
2006
IEEE
15 years 3 months ago
2006
IEEE
Modern network processors support high levels of parallelism in packet processing by supporting multiple threads that execute on a micro-engine. Threads switch context upon encoun...
USENIX
2004
14 years 11 months ago
2004
For operating system intensive applications, the ability of designers to understand system call performance behavior is essential to achieving high performance. Conventional perfo...
USENIX
1993
14 years 11 months ago
1993
Robotic storage devices offer huge storage capacity at a low cost per byte, but with large access times. Integrating these devices into the storage hierarchy presents a challenge ...