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» Designing a DHT for Low Latency and High Throughput
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TVLSI
2008
121views more  TVLSI 2008»
14 years 9 months ago
Area-Efficient Arithmetic Expression Evaluation Using Deeply Pipelined Floating-Point Cores
Recently, it has become possible to implement floating-point cores on field-programmable gate arrays (FPGAs) to provide acceleration for the myriad applications that require high-p...
Ronald Scrofano, Ling Zhuo, Viktor K. Prasanna
HOTI
2008
IEEE
15 years 4 months ago
NoC with Near-Ideal Express Virtual Channels Using Global-Line Communication
As processor core counts increase, networks-on-chip (NoCs) are becoming an increasingly popular interconnection fabric due to their ability to supply high bandwidth. However, NoCs...
Tushar Krishna, Amit Kumar 0002, Patrick Chiang, M...
ASPDAC
2008
ACM
154views Hardware» more  ASPDAC 2008»
14 years 11 months ago
Exploring high-speed low-power hybrid arithmetic units at scaled supply and adaptive clock-stretching
Meeting power and performance requirement is a challenging task in high speed ALUs. Supply voltage scaling is promising because it reduces both switching and active power but it al...
Swaroop Ghosh, Kaushik Roy
114
Voted
DAC
2012
ACM
13 years 3 days ago
Cache revive: architecting volatile STT-RAM caches for enhanced performance in CMPs
Spin-Transfer Torque RAM (STT-RAM) is an emerging non-volatile memory (NVM) technology that has the potential to replace the conventional on-chip SRAM caches for designing a more ...
Adwait Jog, Asit K. Mishra, Cong Xu, Yuan Xie, Vij...
76
Voted
OOPSLA
2004
Springer
15 years 3 months ago
MC2: high-performance garbage collection for memory-constrained environments
Java is becoming an important platform for memory-constrained consumer devices such as PDAs and cellular phones, because it provides safety and portability. Since Java uses garbag...
Narendran Sachindran, J. Eliot B. Moss, Emery D. B...