377 search results - page 4 / 76 » Designing a DHT for Low Latency and High Throughput |
ASPDAC
2010
ACM
14 years 7 months ago
2010
ACM
Asynchronous on-chip networks are power efficient and tolerant to process variation but they are slower than synchronous on-chip networks. A low latency asynchronous wormhole route...
DT
2007
14 years 9 months ago
2007
- This paper presents a new low latency Crossbar design that can be used to interface systems working at different frequencies. For case of multiple input ports contending for same...
ICPP
2007
IEEE
15 years 3 months ago
2007
IEEE
It is a challenge to design and implement a wide-area distributed hash table (DHT) which provides a storage service with high reliability. Many existing systems use replication to...
WMPI
2004
ACM
15 years 3 months ago
2004
ACM
This paper discusses die cost vs. performance tradeoffs for a PIM system that could serve as the memory system of a host processor. For an increase of less than twice the cost of ...
ISCA
2003
IEEE
15 years 2 months ago
2003
IEEE
Designing ASICs for each new generation of backbone routers is a time intensive and fiscally draining process. In this paper we focus on the design of a programmable architecture...