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» Designing a DHT for Low Latency and High Throughput
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76
Voted
DATE
2008
IEEE
133views Hardware» more  DATE 2008»
15 years 4 months ago
Memory Organization with Multi-Pattern Parallel Accesses
We propose an interleaved memory organization supporting multi-pattern parallel accesses in twodimensional (2D) addressing space. Our proposal targets computing systems with high ...
Arseni Vitkovski, Georgi Kuzmanov, Georgi Gaydadji...
COMCOM
2007
84views more  COMCOM 2007»
14 years 9 months ago
A genetic approach for adding QoS to distributed virtual environments
Distributed Virtual Environment (DVE) systems have been designed last years as a set of distributed servers. These systems allow a large number of remote users to share a single 3...
Silvia Rueda, Pedro Morillo, Juan M. Orduña...
VTC
2007
IEEE
159views Communications» more  VTC 2007»
15 years 3 months ago
Data Fragmentation Scheme in IEEE 802.15.4 Wireless Sensor Networks
— The IEEE 802.15.4 Medium Access Control (MAC) protocol is designed for low data rate, short distance and low power communication applications such as Wireless Sensor Networks (...
Jongwon Yoon, Hyogon Kim, Jeong-Gil Ko
77
Voted
ESAS
2004
Springer
15 years 3 months ago
Secure AES Hardware Module for Resource Constrained Devices
Abstract. Low power consumption, low gate count, and high throughput are standard design criteria for cryptographic coprocessors designated for resource constrained devices such as...
Elena Trichina, Tymur Korkishko
MONET
2007
126views more  MONET 2007»
14 years 9 months ago
Performance Evaluation of a Power Management Scheme for Disruption Tolerant Network
Disruption Tolerant Network (DTN) is characterized by frequent partitions and intermittent connectivity. Power management issue in such networks is challenging. Existing power man...
Yong Xi, Mooi Choo Chuah, K. Chang