377 search results - page 58 / 76 » Designing a DHT for Low Latency and High Throughput |
HIPEAC
2007
Springer
15 years 3 months ago
2007
Springer
A critical component in the design of secure processors is memory encryption which provides protection for the privacy of code and data stored in off-chip memory. The overhead of ...
ICPP
1999
IEEE
15 years 1 months ago
1999
IEEE
This paper presents a mesh with virtual buses as the bandwidth-efficient implementation of the mesh with multiple broadcasting on which many computational problems can be solved w...
MOBICOM
2005
ACM
15 years 3 months ago
2005
ACM
This paper evaluates the ability of a wireless mesh architecture to provide high performance Internet access while demanding little deployment planning or operational management. ...
HPCA
2005
IEEE
15 years 10 months ago
2005
IEEE
With the increasing concern of the security on high performance multiprocessor enterprise servers, more and more effort is being invested into defending against various kinds of a...
NOCS
2007
IEEE
15 years 3 months ago
2007
IEEE
Dynamic routing can substantially enhance the quality of service for multiprocessor communication, and can provide intelligent adaptation of faulty links during run time. Implemen...