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» Designing a DHT for Low Latency and High Throughput
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DASC
2006
IEEE
15 years 3 months ago
On Recognizing Virtual Honeypots and Countermeasures
— Honeypots are decoys designed to trap, delay, and gather information about attackers. We can use honeypot logs to analyze attackers’ behaviors and design new defenses. A virt...
Xinwen Fu, Wei Yu, Dan Cheng, Xuejun Tan, Kevin St...
74
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IPPS
2006
IEEE
15 years 3 months ago
A study of the on-chip interconnection network for the IBM Cyclops64 multi-core architecture
The designs of high-performance processor architectures are moving toward the integration of a large number of multiple processing cores on a single chip. The IBM Cyclops-64 (C64)...
Yingping Zhang, Taikyeong Jeong, Fei Chen, Haiping...
IWNAS
2008
IEEE
15 years 4 months ago
A Novel Embedded Accelerator for Online Detection of Shrew DDoS Attacks
∗ As one type of stealthy and hard-to-detect attack, lowrate TCP-targeted DDoS attack can seriously throttle the throughput of normal TCP flows for a long time without being noti...
Hao Chen, Yu Chen
CODES
2006
IEEE
15 years 3 months ago
Bounded arbitration algorithm for QoS-supported on-chip communication
Time-critical multi-processor systems require guaranteed services in terms of throughput, bandwidth etc. in order to comply to hard real-time constraints. However, guaranteedservi...
Mohammad Abdullah Al Faruque, Gereon Weiss, Jö...
AINA
2009
IEEE
15 years 2 months ago
Effects of On-path Buffering on TCP Fairness
Keeping router buffering low helps minimise delay (as well as keeping router costs low), whilst increasing buffering minimises loss. This is a trade-off for which there is no sing...
Saleem N. Bhatti, Martin Bateman