377 search results - page 62 / 76 » Designing a DHT for Low Latency and High Throughput |
ASAP
2004
IEEE
15 years 1 months ago
2004
IEEE
Large register file with multiple ports is a critical component of a high-performance processor. A large number of registers are necessary for processing a larger number of in-fli...
194
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CCGRID
2011
IEEE
14 years 1 months ago
2011
IEEE
— A key advantage of Infrastructure-as-a-Service (IaaS) clouds is providing users on-demand access to resources. However, to provide on-demand access, cloud providers must either...
OTM
2009
Springer
15 years 4 months ago
2009
Springer
Complex event processing (CEP) is a software architecture paradigm that aims at low latency, high throughput, and quick adaptability of applications for supporting and improving ev...
LCPC
2005
Springer
15 years 3 months ago
2005
Springer
Programming network processors remains a challenging task since their birth until recently when high-level programming environments for them are emerging. By employing domain speci...
110
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DATE
2010
IEEE
15 years 2 months ago
2010
IEEE
Networks-on-Chip (NoCs) are a promising interconnect paradigm to address the communication bottleneck of Systems-on-Chip (SoCs). Wormhole flow control is widely used as the trans...